In modern satellite navigation systems, such as the Global Positioning System (GPS), satellites transmit a code division multiple access (CDMA) signal in which the spectrum of a data signal has been spread prior to transmission by multiplying the data signal by a code, specifically a pseudo-random code. A receiver for such systems employs a correlator to correlate a received signal with the code in order to recover the data signal. The correlation entails forming the product of the received signal with the code, and summing the product over an integration period.
As different satellites use different codes, and as the phase of each code is not known at the receiver, many correlators, typically several hundred, are run in parallel.
FIG. 1 illustrates a typical correlator 100 comprising a multiplication stage 150 and an accumulation stage 160. The multiplication stage 150 comprises a multiplier 110 having a first input 112 for a correlator input signal and a second input 114 for a pseudo-random code generated by a code generator 120. The multiplier 110 multiplies the correlator input signal by the pseudo-random code. The accumulation stage 160 comprises a summing stage 130 and a register 140. An output 116 of the multiplier 110 is coupled to a first input 132 of the summing stage 130. A second input 134 of the summing stage 130 is supplied with the result of previous summations. An output 136 of the summing stage 130 is coupled to the register 140 which stores the result of summing by the summing stage 130. An output 146 of the register 140 is coupled to the second input 134 of the summing stage 130 for delivering the result of previous summations.
Typically, the accumulation stage 160 comprises synchronous registers. Such a solution can require a large chip area when implemented in an integrated circuit, due to the requirement for a balanced clock tree and a dedicated scan structure, meaning that many clock buffers are needed for distributing a clock signal in a balanced way, and also such a solution can have a high power consumption. Moreover, the accumulation stage 160 potentially has a high electromagnetic emission due to the large amount of digital logic clocked simultaneously.